The present invention relates to dedicated block random access memory (RAM) located on a programmable logic device, such as a field programmable gate array (FPGA).
FPGAs typically include an array of configurable logic blocks (CLBs), input/output blocks (IOBs) and programmable interconnect circuitry that extends between the CLBs and IOBs. Some FPGAs include dedicated columns of block RAM which are located between columns of the CLBs. Such block RAM provides a relatively high-density memory. In the absence of the block RAM, memory could be provided by configuring the CLBs in an appropriate manner. However, a relatively large number of CLBs are required to provide a small memory, thereby resulting in an inefficient use of FPGA resources. An FPGA that includes block RAM is described in U.S. Pat. No. 5,933,023.
The block RAMs present in the above-identified FPGAs are not capable of storing data values with parity bits. Thus, the block RAMs of conventional FPGAs have been undesirably limited to a non-parity configuration. Providing for parity configurations when word width is fairly large would advantageously provide the user with more flexibility to suit their application needs.
It would therefore be desirable to have a dual-port block RAM with selectable parity and non-parity configurations.
Accordingly, the present invention provides an FPGA that includes a block RAM having selectable parity and non-parity configurations. The block RAM includes a memory cell array and control logic that is configurable to select one of a plurality of parity and non-parity configurations for storing data in the memory cell array. In one embodiment, the block RAM includes a 144 columnxc3x97128 row array of dual-port memory cells. One embodiment of the array allows for word lengths (data widths) of 1, 2, 4, 9, 18, and 36 bits. The 9, 18, and 36-bit words allow for convenient addition of 1, 2, and 4 parity bits, respectively, if desired by the user and also allow for 8, 16, and 32-bit words if the user does not choose to use parity. Yet with no use of parity, a rather small amount of memory goes unused.
The present invention treats the 18-bit unit as two blocks of RAM, a 16-bit block and a 2-bit block and allows particularly efficient use of all the memory bits. When the RAM is being configured in a shallow configuration 1 or 2 bits wide, access is granted to the shallower (2-bit) blocks, thus making full use of the memory space.
The control logic selects the parity/non-parity configurations in response to configuration bits stored in corresponding configuration memory cells of the FPGA. The configuration bits are typically programmed during configuration of the PLD.
In a particular embodiment, the block RAM is a dual-port memory having a first port and a second port. In this embodiment, the first and second ports can be independently configured to have different (or the same) parity/non-parity configurations. The widths of the first and second ports can also be independently configured.
Mapping data between ports of different data widths becomes non-trivial when the parity block is added. The invention allows the memory array to be operated at widths that are multiples of 9 bits and allows both parity and non-parity modes to be efficiently used (see FIGS. 8-11).
The present invention will be more fully understood in view of the following description and drawings.